(1) Field of the Invention
The present invention relates to a driver circuit for driving a plasma display panel (PDP) or the like.
(2) Description of the Related Art
As shown in FIG. 1, a conventional PDP driver includes a level shift unit 25, a CMOS output unit 26 and a low voltage control unit 21.
The level shift unit 25 includes a PMOS transistor 17 and a PMOS transistor 16. The sources of the transistors 17 and 16 are both connected to a high voltage power supply terminal 22, the drains thereof are respectively connected to a contact IN5 and a contact IN4, and the gate of one transistor is connected to the drain of the other transistor crosswise. The level shift unit 25 further includes an NMOS transistor 20 and an NMOS transistor 19. The gates of these transistors 20 and 19 are respectively connected to one of a contact IN1 and IN2 of the low voltage control unit 21, the drains thereof are respectively connected to the contact IN5 and the contact IN4, and the sources thereof are both grounded.
The CMOS output unit 26 includes an NMOS transistor 18 and a PMOS transistor 15. The gate of the NMOS transistor 18 is connected to a contact IN3 of the low voltage control unit 21, the drain thereof is connected to an output terminal 24, and the source thereof is grounded, while the source of the PMOS transistor is connected to the high voltage power supply terminal 22, the gate thereof is connected to the contact IN4, and the drain thereof is connected to the output terminal 24.
The low voltage control unit 21 is connected to a low voltage power supply terminal 27. An output load 34 is a capacitive load like a plasma display panel.
FIG. 2 shows the waveforms of the input and output signals of the low voltage control unit 21 in the conventional PDP driver and the signals at the contacts IN4, IN5 and the output terminal 24.
Next, the operation of the conventional PDP driver is described below. It is assumed here that the signal IN inputted to the low voltage control unit 21 switches from High (VDD level in this case) to Low (GND level in this case). In this case, the NMOS transistor 20 is turned on by the signal IN1 inputted from the low voltage control unit 21 and the potential of the contact IN5 drops to the ground potential (GND), which turns on the PMOS transistor 16. At the same time as the turn-on of the PMOS transistor 16, the NMOS transistor 16 is turned off by the signal IN2 inputted from the low voltage control unit 21, and as a result, the potential of the contact IN4 rises to the potential level of the high voltage power supply (VDDH), which turns off the PMOS transistor 15. Furthermore, the NMOS transistor 18 is turned on by the signal IN3 inputted from the low voltage control unit 21, which causes the potential of the output terminal 24 to drop to the ground potential (GND).
Reversely, when the IN signal switches from High to Low, the NMOS transistor 19 is turned on by the signal IN2 inputted from the low voltage control unit 21. At the same time as the turn-on of the NMOS transistor 19, the NMOS transistor 20 is turned off, the PMOS transistor 17 is turned on and the PMOS transistor 16 is turned off by the signal IN1. At that time, the potential of the contact IN4 drops to the ground potential (GND), which turns on the PMOS transistor 15. As a result, the potential of the output terminal 24 rises to the potential level of the high voltage power supply (VDDH), and the NMOS transistor 18 is turned off by the signal IN3.
In this case, the driving capability of each transistor in the level shift unit 25 is determined as follows.
The PMOS transistor 16 and the NMOS transistor 19 of which drains are connected to the CMOS output unit 26 have heavier driving load than the PMOS transistor 17 and the NMOS transistor 20 which are placed at the front side in the level shift unit 25 because the PMOS transistor 16 and the NMOS transistor 19 drive the CMOS output unit 26. Therefore, the PMOS transistor 16 and the NMOS transistor 19 need to have higher driving capability than the PMOS transistor 17 and the NMOS transistor 20 (See Examined Japanese Patent Application Publication No. 6-91442).
When the potentials of IN4 and IN5 in the level shift unit 25 switch from High (VDDH level in this case) to Low (GND level in this case) and vice versa, namely from Low to High, pass-through current flows transiently through the PMOS transistor 17 and the NMOS transistor 20 and through the PMOS transistor 16 and the NMOS transistor 19, respectively. In order to reduce this pass-through current, the potentials of IN4 and IN5 must be immediately switched to the potentials of stable values. Therefore, the NMOS transistors 20 and 19 need to have higher driving capabilities than the PMOS transistors 17 and 16 (See Laid-Open Patent Application Publication No. 2000-164730).
As described above, in the conventional PDP driver, the pass-through current hardly flows through the level shift unit 25 and the CMOS output unit 26 if the power supply voltage VDD supplied from the low voltage power supply to the low voltage power supply terminal 27 is within a range of recommended operating power supply voltages, that is, within a range of power supply voltages which ensure the normal operation of the circuit, and therefore the desired operation is achieved.
However, the power supply voltage VDD supplied from the low voltage power supply to the low voltage power supply terminal 27 may be maintained around the medium potential VLo that is lower than the rated value because the low voltage power supply is not started up or shut down immediately when the power is turned on or off. For example, in the case where the rated value of the power supply voltage VDD is 5V, when the power is turned on, the power supply voltage VDD supplied from the low voltage power supply to the low voltage power supply terminal 27 is sometimes maintained around the medium potential VLo of 2V during the transition in which the voltage VDD is turned off. In this case where the power supply voltage VDD which has been supplied from the low voltage power supply to the low voltage power supply terminal 27 becomes lower than the recommended operating power supply voltage and the High levels of IN1, IN2 and IN3 drop, the circuit operates differently from the above-mentioned desired operation.
As shown in FIG. 3, when an input voltage IN switches from High (VLo level in this case) to Low (GND level in this case), the input voltage IN1 of the level shift unit 25 turns into High, so that the NMOS transistor 20 is turned on and the PMOS transistor 16 is turned on. On the contrary, the input voltage IN2 of the level shift unit 25 turns into Low, so that the NMOS transistor 19 is turned off and the PMOS transistor 17 is turned off. If the power supply voltage VDD drops, it becomes impossible to secure the input voltage IN1 that is sufficiently larger than the threshold voltage (VT) of the NMOS transistor 20. Therefore, the potential of the contact IN5 cannot switch to Low instantaneously and there is a period of time t0 during which the potential of the contact IN5 stays at the medium potential 1 (VDDL level in this case).
On the other hand, the driving capability of the PMOS transistor 16 is lower than that of the NMOS transistor 19. In addition, since the potential of the contact IN5 is not Low but stays at the medium potential 1 (VDDL level) during the period t0, the PMOS transistor 16 is in an incomplete ON state and thus its driving current is reduced. Therefore, the PMOS transistor 16 which is in the incomplete ON state cannot supply the current sufficiently larger than the current driven by the NMOS transistor 19 which is in an incomplete OFF state, and thus the PMOS transistor 16 cannot be turned on instantaneously. As a result, the potential of the contact IN4 does not rise from Low (GND level in this case) to High (VDDH level in this case) immediately and there is a period of time t0 during which it stays at the medium potential 2 (VDDM level in this case).
During this period t0, the PMOS transistor 15 of the CMOS output unit 26 cannot be turned off completely due to the potential at the contact IN4, and the NMOS transistor 18 of the CMOS output unit 26 is in an ON state by the input signal from IN3. As a result, both the PMOS transistor 15 and the NMOS transistor 18 of the CMOS output unit 26 are turned on, and therefore the potential of the output terminal 24 does not drop completely to the ground potential but stays at the medium potential (VoutM level in this case). Therefore, a large amount of pass-through current flows from the high voltage power supply (VDDH) side to the ground potential (GND) side of the CMOS output unit 26. This pass-through current causes a breakdown of the PDP driver and the image deterioration of the plasma display panel.
This problem is very serious particularly when the power supplied to the PDP driver is turned off. As shown in FIG. 4, after the power is turned off, the voltage of the low voltage power supply VDD declines with a small time constant (namely, fast), while the voltage of the high voltage power supply VDDH declines with a large time constant (namely, slowly), according to the amount of load put on the high voltage power supply VDDH and the low voltage power supply VDD, respectively. Therefore, the gate voltage of the NMOS transistor 20 declines fast while the high voltage is being supplied from the high voltage power supply VDDH to the CMOS output unit 26, and the PMOS transistor 15 is not turned off completely, which results in a flow of pass-through current in the CMOS output unit 26.